0.9 V third‐order 132 MHz single‐OPAMP analogue filter in 28 nm CMOS. Issue 2 (1st January 2017)

• Record Type: Journal Article
• Authors: De Matteis, M.; Donno, A.; D'Amico, S.; Baschirotto, A.
• Is Part Of: Electronics letters. Volume 53:Issue 2(2017)
• Page Start: 77
• Page End: 79
• Publication Date: 2017-01-01
• Subjects: CMOS analogue integrated circuits -- VHF filters -- operational amplifiers -- VHF amplifiers -- low‐pass filters -- integrated circuit design; third‐order single‐OPAMP analogue filter -- CMOS‐bulk lowpass analogue filter architecture -- improved active‐Gm‐RC structure -- Miller‐compensated OPAMP -- signal‐to‐noise ratio -- SNR -- power consumption -- figure‐of‐merit -- voltage 0.9 V -- frequency 132 MHz -- size 28 nm -- power 340 muW; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2016.3273
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A 28 nm CMOS‐bulk lowpass analogue filter architecture is hereby proposed. The filter is based on an improved Active‐ Gm ‐RC structure, where both poles of a Miller‐compensated operational amplifier (OPAMP) have been used for synthesising a third‐order filter. Several well‐known issues related to the 28 nm process node have been hereby mitigated by proper circuit/design techniques, enabling large signal‐to‐noise ratio (SNR) and 13.5 dBm IIP3. The proposed circuital solution performs 59 dB‐SNR at 340 µW power consumption from a single 0.9 V supply‐voltage. This allows one of the higher figure‐of‐merit (156 dB) in sub‐1 V analogue filters state of the art.