Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source. Issue 4 (17th April 2020)

• Record Type: Journal Article
• Authors: Azimi, Nooshin; Mirzaee, Reza Faghih; Navi, Keivan; Rahmani, Amir Masoud
• Is Part Of: IET computers & digital techniques. Volume 14:Issue 4(2020)
• Page Start: 166
• Page End: 175
• Publication Date: 2020-04-17
• Subjects: logic gates -- logic design -- logic circuits -- ternary logic -- low‐power electronics -- carbon nanotube field effect transistors -- field effect transistor circuits -- redundancy; combined dynamic logic style -- standard ternary logic -- single power source -- differential cascode voltage switch logic -- ideal logic style -- error detection applications -- ternary static DCVSL -- ternary dynamic DCVSL -- static‐to‐dynamic conversion method -- binary logic -- static power dissipation -- power consumption -- ternary circuit methodology -- Stanford carbon nanotube field effect transistor model -- static ternary logic styles -- SDCVSL -- switching activity -- HSPICE simulator -- ternary DDCVSL AND‐NAND -- energy consumption -- size 32.0 nm; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2019.0216
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static‐to‐dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state‐of‐the‐art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS‐like, SDCVSL, and pseudo N‐type, respectively, in terms of energy consumption.