Architecture of a real‐time delay calculator for digital beamforming in ultrasound system. Issue 4 (1st July 2016)

• Record Type: Journal Article
• Authors: Agarwal, Mayur; De, Arijit; Banerjee, Swapna
• Is Part Of: IET circuits, devices & systems. Volume 10:Issue 4(2016)
• Page Start: 322
• Page End: 329
• Publication Date: 2016-07-01
• Subjects: transducers -- approximation theory -- ultrasonic imaging -- array signal processing; real-time delay calculator -- digital beamforming -- ultrasound system -- synthetic transmit aperture -- phased array imaging -- dynamic focusing -- multielement transducer array -- on-line computation -- hardware architecture -- 64-element convex transducer array -- scan lines -- scan points -- hardware consumption -- 28-bit radicand hybrid square root calculator -- linear approximation -- quadratic approximation -- cyst image phantoms -- Matlab -- Field II toolbox; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2015.0189
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In ultrasound systems synthetic transmit aperture and phased array imaging are widely used for obtaining the high quality images. These imaging systems require dynamic focusing of the multi‐element transducer array at large number of scan points during transmission and reception. The array can be focused at any point by applying proper delay values to the signals, received or transmitted by each element of the array. Dynamic focusing requires on‐line computation of the delay values, for large number of scan points, corresponding to all the elements of the array. This paper describes a delay calculation algorithm and corresponding hardware architecture for dynamically focusing the convex transducer array at large number of scan points. The hardware architecture for the 64‐element convex transducer array, which scans 128 scan lines having 1024 scan points on each scan line, consumes 61k gates. It shows around 57–86% improvement in terms of hardware consumption with respect to those of other available architectures. To reduce the overall complexity and latency of the delay calculator, a 28‐ bit radicand square root calculator architecture which requires less initial memory than that of the linear approximation and less hardware resources than that of the quadratic approximation is also presented.