Wide‐range (25 ns) and high‐resolution (48.8 ps) clock phase shifter. Issue 10 (1st May 2013)

• Record Type: Journal Article
• Authors: Wu, Guoying; Yu, Bryan; Gui, Ping; Moreira, P.
• Is Part Of: Electronics letters. Volume 49:Issue 10(2013)
• Page Start: 642
• Page End: 644
• Publication Date: 2013-05-01
• Subjects: clocks -- CMOS logic circuits -- delay lock loops -- phase shifters; high‐resolution clock phase shifter -- wide‐range clock phase shifter -- CMOS technology -- power consumption -- coarse‐fine two‐step phase shifting structure -- delay‐locked loop -- unconventional clock input setup -- fine‐shifting stage -- time 25 ns -- time 48.8 ps -- size 0.13 mum; clocks -- CMOS logic circuits -- delay lock loops -- phase shifters; high‐resolution clock phase shifter -- wide‐range clock phase shifter -- CMOS technology -- power consumption -- coarse‐fine two‐step phase shifting structure -- delay‐locked loop -- unconventional clock input setup -- fine‐shifting stage -- time 25 ns -- time 48.8 ps -- size 0.13 mum; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2012.4274
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A wide‐range (25 ns), high‐resolution (48.8 ps) clock phase shifter developed and fabricated using a 0.13 µm CMOS technology is presented. To achieve both wide range and high resolution with good linearity while minimising area and power consumption, a coarse–fine two‐step phase‐shifting structure is proposed. A delay‐locked loop with an unconventional clock input setup is used in the fine‐shifting stage to ahieve the high resolution. Test results show that the standard deviations of the differential nonlinearity and integral nonlinearity are 4.7 ps and 4.3 ps, respectively.