22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time‐to‐digital converter in CMOS 65 nm for single photon avalanche diode array. Issue 9 (1st April 2020)

• Record Type: Journal Article
• Authors: Nolet, F.; Roy, N.; Carrier, S.; Bouchard, J.; Fontaine, R.; Charlebois, S.A.; Pratte, J.‐F.
• Is Part Of: Electronics letters. Volume 56:Issue 9(2020)
• Page Start: 424
• Page End: 426
• Publication Date: 2020-04-01
• Subjects: timing jitter -- positron emission tomography -- readout electronics -- time‐digital conversion -- avalanche photodiodes -- photodetectors -- biomedical electronics -- CMOS logic circuits; LSB -- CMOS -- single photon avalanche diode array -- Vernier ring‐oscillator‐based time‐to‐digital converter -- prelogic circuit -- power consumption -- TDC -- position emission tomography single photon avalanche diode based detectors -- RMS jitter Vernier time‐to‐digital converter -- RMS timing jitter -- dynamic range -- electronic readout -- time 5.5 ps -- time 5.1 ps -- time 4.0 ns -- power 22.0 muW -- size 65.0 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2019.4105
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A Vernier ring‐oscillator‐based time‐to‐digital converter (TDC) with a new prelogic is presented. Experimental results show that the proposed architecture achieve a 5.5 ps RMS timing jitter with a 5.1 ps LSB within an area of 0.00151 mm 2 . Thanks to the new prelogic circuit, the power consumption of the circuit was optimised to 22 μ W at a rate of 1 Mevents/s for a dynamic range of 4 ns. The area, timing jitter and power consumption make the TDC suitable for an array of electronic readout in a position emission tomography single photon avalanche diode based detectors.