Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher. Issue 2 (9th January 2020)

• Record Type: Journal Article
• Authors: Rashidi, Bahram
• Is Part Of: IET computers & digital techniques. Volume 14:Issue 2(2020)
• Page Start: 69
• Page End: 79
• Publication Date: 2020-01-09
• Subjects: cryptography -- logic gates -- logic circuits; flexible hardware structures -- flexible hardware implementations -- CLEFIA lightweight block cipher -- unified processing element -- generalised Feistel network -- encryption process -- separate times -- complex blocks -- CLEFIA algorithm -- substitution boxes -- area‐optimised combinational logic circuits -- S‐box structure -- logic gates -- critical path delay -- computation terms -- field inversion -- affine transformations -- inversion operation -- area consumption -- efficient structure -- composite field -- gate level -- flexible structure -- variable key size -- versatile implementation -- word length 128.0 bit -- size 180.0 nm -- word length 192.0 bit -- word length 256.0 bit; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2019.0157
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : In this study, high‐throughput and flexible hardware implementations of the CLEFIA lightweight block cipher are presented. A unified processing element is designed and shared for implementing of generalised Feistel network that computes round keys and encryption process in the two separate times. The most complex blocks in the CLEFIA algorithm are substitution boxes ( S 0 and S 1 ). The S 0 S‐box is implemented based on area‐optimised combinational logic circuits. In the proposed S‐box structure, the number of logic gates and critical path delay are reduced by using the simplification of computation terms. The S‐box S 1 consists of three steps: a field inversion over F 2 8 and two affine transformations over F 2 . The inversion operation is implemented over the composite field F ( 2 4 ) 2 instead of inversion over F 2 8 which is an important factor for the reduction of area consumption. In addition, we proposed a flexible structure that can perform various configurations of CLEFIA to support variable key sizes: 128, 192 and 256 bit. Implementation results of the proposed architectures in 180 nm complementary metal–oxide–semiconductor technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared with other related works.