VLSI design of low‐cost and high‐precision fixed‐point reconfigurable FFT processors. Issue 3 (11th April 2018)

• Record Type: Journal Article
• Authors: Xiao, Hao; Yin, Xiang; Wu, Ning; Chen, Xin; Li, Jun; Chen, Xiaoxing
• Is Part Of: IET computers & digital techniques. Volume 12:Issue 3(2018)
• Page Start: 105
• Page End: 110
• Publication Date: 2018-04-11
• Subjects: VLSI -- integrated circuit design -- fast Fourier transforms -- signal denoising -- quantisation (signal) -- statistical analysis -- optimisation; VLSI design -- low‐cost high‐precision fixed‐point reconfigurable FFT processors -- fast Fourier transform -- very large‐scale integration -- digital signal processing systems -- FFT computation -- quantisation noise -- scaling approach -- statistics‐based optimisation scheme -- signal‐to‐quantisation‐noise ratio; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2017.0060
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Fast Fourier transform (FFT) plays an important role in digital signal processing systems. In this study, the authors explore the very large‐scale integration (VLSI) design of high‐precision fixed‐point reconfigurable FFT processor. To achieve high accuracy under the limited wordlength, this study analyses the quantisation noise in FFT computation and proposes the mixed use of multiple scaling approaches to compensate the noise. In addition, a statistics‐based optimisation scheme is proposed to configure the scaling operations of the cascaded arithmetic blocks at each stage for yielding the most optimised accuracy for a given FFT length. On the basis of this approach, they further present a VLSI implementation of area‐efficient and high‐precision FFT processor, which can perform power‐of‐two FFT from 32 to 8192 points. By using the SMIC 0.13 μ m process, the area of the proposed FFT processor is 27 m m 2 with a maximum operating frequency of 400 MHz. When the FFT processor is configured to perform 8192‐point FFT at 40 MHz, the signal‐to‐quantisation‐noise ratio is up to 53.28 dB and the power consumption measured by post‐layout simulation is 35.7 mW.