Very‐large‐scale integration implementation of a 16‐bit clocked adiabatic logic logarithmic signal processor. Issue 5 (1st September 2015)

• Record Type: Journal Article
• Authors: Yemiscioglu, Gurtac; Lee, Peter
• Is Part Of: IET computers & digital techniques. Volume 9:Issue 5(2015)
• Page Start: 239
• Page End: 247
• Publication Date: 2015-09-01
• Subjects: VLSI -- logic design -- digital signal processing chips -- low‐power electronics -- clocks -- integrated circuit design -- CMOS integrated circuits; very‐large‐scale integration implementation -- clocked adiabatic logic logarithmic signal processor -- low‐power logarithmic signal processor -- Austria Micro Systems -- complementary metal oxide semiconductor process -- processor architecture -- clock frequencies -- CMOS logic; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2014.0102
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : This study describes a low‐power 16‐bit logarithmic signal processor built using clocked adiabatic logic. The circuit has been designed and implemented using an Austria Micro Systems 0.35 μm complementary metal–oxide–semiconductor (CMOS) process. A test device has been fabricated and functionally verified. The processor architecture has an active area of 0.57 mm 2 . Simulation results with this architecture, using clock frequencies up to 100 MHz have confirmed results from other researchers that clocked adiabatic consumes up to ten times less power than conventional CMOS logic.