Improved dual‐capacitive arrays DAC architecture for SAR ADC. Issue 12 (1st June 2016)

• Record Type: Journal Article
• Authors: Li, Dong; Meng, Qiao; Li, Fei
• Is Part Of: Electronics letters. Volume 52:Issue 12(2016)
• Page Start: 1013
• Page End: 1015
• Publication Date: 2016-06-01
• Subjects: analogue‐digital conversion; average switching energy -- reference voltage -- switching‐back switching scheme -- successive approximation register -- IDCA‐DAC architecture -- SAR ADC -- improved dual‐capacitive arrays DAC architecture; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2016.0203
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : An improved dual‐capacitive arrays DAC (IDCA‐DAC) architecture for successive approximation register ADC is presented. By using a switching‐back switching scheme and a third reference voltage for the last bit conversion, the proposed IDCA‐DAC architecture achieves 42% savings in average switching energy and 47.1% reduction in area compared with the original DCA‐DAC architecture. Additionally, it can achieve 99.3% savings in average switching energy and 71.9% reduction in area compared with the conventional method.