Evanescent mode based compact modelling of a dual‐metal double‐gate tunnel field‐effect transistor. Issue 7 (23rd October 2020)

• Record Type: Journal Article
• Authors: Bose, Ria; Roy, Jatindra Nath
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 7(2020)
• Page Start: 1032
• Page End: 1037
• Publication Date: 2020-10-23
• Subjects: technology CAD (electronics) -- silicon -- elemental semiconductors -- semiconductor device models -- tunnel field‐effect transistors; compact modelling -- channel potential -- evanescent‐mode approach -- sub‐threshold region -- short channel effects -- channel region -- device structure -- characteristic length -- tunnel current -- Kleysh model -- silicon‐based doped double‐gate tunnel field‐effect transistor structure -- bias condition -- drain current -- Kane model -- 2D TCAD Sentaurus simulator -- Si; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0531
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In this study, channel potential for silicon‐based doped dual‐metal double‐gate tunnel field‐effect transistor structure is analytically solved using the evanescent‐mode approach in the sub‐threshold region. This method generally describes short channel effects in the entire channel region of the device structure and predicts different characteristic length λ which depends on tunnel current and does not depend along a transverse direction within the channel. The model is valid for the whole device structure rather than just semiconductor/insulator interfaces. The impact of variation of bias condition on channel potential is also investigated in the sub‐threshold region. Finally, drain current is evaluated using Kane's and Kleysh's model and validated with a calibrated simulation, which has been carried out using 2D TCAD Sentaurus simulator.