Locality‐protected cache allocation scheme with low overhead on GPUs. Issue 3 (12th January 2018)

• Record Type: Journal Article
• Authors: Zhang, Yang; Xing, Zuocheng; Tang, Chuan; Liu, Cang
• Is Part Of: IET computers & digital techniques. Volume 12:Issue 3(2018)
• Page Start: 87
• Page End: 94
• Publication Date: 2018-01-12
• Subjects: cache storage -- resource allocation -- graphics processing units -- parallel processing -- energy conservation; locality‐protected cache allocation scheme -- low overhead -- GPU -- graphics processing units -- parallel computing -- multithreaded execution model -- parallel programmes -- energy saving -- on‐chip memory space -- throughput‐oriented execution model -- hardware threads -- cache thrashing -- contention problems -- instruction programme counter -- LPC -- data locality -- L1 data cache -- PC‐based locality detector -- cache line -- hardware‐efficient prioritised cache allocation unit -- data reuse information -- time‐stamp information -- least reuse possibility; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2017.0004
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Graphics processing units (GPUs) are playing more important roles in parallel computing. Using their multi‐threaded execution model, GPUs can accelerate many parallel programmes and save energy. In contrast to their strong computing power, GPUs have limited on‐chip memory space which is easy to be inadequate. The throughput‐oriented execution model in GPU introduces thousands of hardware threads, which may access the small cache simultaneously. This will cause cache thrashing and contention problems and limit GPU performance. Motivated by these issues, the authors put forward a locality‐protected method based on instruction programme counter (LPC) to make use of data locality in L1 data cache with very low hardware overhead. First, they use a simple Program Counter (PC)‐based locality detector to collect reuse information of each cache line. Then, a hardware‐efficient prioritised cache allocation unit is proposed to coordinate data reuse information with time‐stamp information to predict the reuse possibility of each cache line, and to evict the line with the least reuse possibility. Their experiment on the simulator shows that LPC provides an up to 17.8% speedup and an average of 5.0% improvement over the baseline method with very low overhead.