CFE: a convenient, flexible, and efficient clocking scheme for quantum‐dot cellular automata. Issue 1 (13th January 2020)

• Record Type: Journal Article
• Authors: Deng, Feifei; Xie, Guangjun; Cheng, Xin; Zhang, Zhang; Zhang, Yongqiang
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 1(2020)
• Page Start: 88
• Page End: 92
• Publication Date: 2020-01-13
• Subjects: logic design -- cellular automata -- clocks -- quantum dots -- electronic design automation; convenient clocking scheme -- quantum-dot cellular automata -- digital circuit designs -- QCA circuit design -- clock distribution -- transmission lines -- clock schemes -- electronic design automation -- complex circuits -- neighbouring clock zone -- circuit design process -- CFE scheme -- standard clock mechanism -- flexible clocking scheme -- information transmission directions; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0096
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Quantum‐dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit designs. The circuits in QCA have been extensively studied, which suffer from negative impacts due to the limits of the manual design process, even for a modest complexity. In the process of QCA circuit design, the problems caused by clock distribution and long transmission lines have to be considered. In order to solve such problems, some researchers have proposed several clock schemes and expected to realise electronic design automation. These clock schemes, however, have drawbacks; the most important one is the limitation of flexibility on designing complex circuits. In this regard, this study proposes a convenient, flexible, and efficient (CFE) clocking scheme by using diamond structures for clock zones, each of which has the same neighbouring clock zone and four information transmission directions. It has main advantages of existing clocking schemes and can commendably increase the flexibility in circuit design process. In order to show the suitability of the proposed CFE scheme using standard clock mechanism in QCA, several types of circuits proposed in this study reveal its advantages in comparison with an existing state‐of‐the‐art clocking scheme.