Low‐power TDC scheme using DLL‐based gray counter for infrared imagers. Issue 14 (1st July 2017)

• Record Type: Journal Article
• Authors: Liu, Dahe; Lu, Wengao; Yu, Shanzhe; Chen, Zhongjian
• Is Part Of: Electronics letters. Volume 53:Issue 14(2017)
• Page Start: 922
• Page End: 924
• Publication Date: 2017-07-01
• Subjects: infrared imaging -- time‐digital conversion -- delay lock loops -- CMOS digital integrated circuits -- clocks; low‐power scheme -- time‐to‐digital converter scheme -- column‐level single‐slope analogue‐to‐digital converters -- timing precision -- delay‐lock‐loop -- DLL‐based grey counter -- multiphase clocks -- array size uncooled infrared imager -- CMOS technology -- two‐step TDC methods -- simulated least‐significant‐bit differential nonlinearity performance -- size 0.18 mum; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2017.0878
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A low‐power time‐to‐digital converter (TDC) scheme for column‐level single‐slope analogue‐to‐digital converters for infrared imager is presented. This scheme greatly improves the TDC's timing precision with a novel 3‐bit fine gray counter, which makes use of multi‐phase clocks from a delay‐lock‐loop. Aimed for 384 × 288 array size uncooled infrared imager with 17 μm pixel pitch, the TDC circuits have been developed and simulated employing 0.18 μm CMOS technology. Compared with conventional two‐step TDC methods, this method saves more chip area and reduces the sampling power consumption by >50%, and also eliminates the coarse‐fine inconsistency problem with a simulated ±0.1 least‐significant‐bit differential non‐linearity performance.