Area–delay and energy efficient multi‐operand binary tree adder. Issue 5 (1st June 2020)

• Record Type: Journal Article
• Authors: Patel, Sujit Kumar; Singhal, Subodh Kumar
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 5(2020)
• Page Start: 586
• Page End: 593
• Publication Date: 2020-06-01
• Subjects: digital arithmetic -- logic design -- adders -- multiplying circuits -- trees (mathematics) -- low-power electronics -- carry logic -- minimisation; Wallace tree adder -- multioperand adders -- BTA design -- energy efficient digital systems -- logic formulation -- RCA design -- 32-operand BTA -- energy–delay product -- ripple carry adder-based binary tree adder -- RCA-based BTA -- multiplier designs; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0443
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Here, the critical path of ripple carry adder (RCA)‐based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing RCA. Using this RCA design, the BTA structure is proposed. The synthesis result reveals that the proposed 32‐operand BTA provides the saving of 22.5% in area–delay product and 28.7% in energy–delay product over the recent Wallace tree adder which is the best among available multi‐operand adders. The authors have also applied the proposed BTA in the recent multiplier designs to evaluate its performance. The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA. Therefore, the proposed BTA design can be a better choice to develop the area, delay and energy efficient digital systems for signal and image processing applications.