Flash ADC‐based digital LDO with non‐linear decoder and exponential‐ratio array. Issue 10 (1st May 2019)

• Record Type: Journal Article
• Authors: Ding, Zhendong; Xu, Xinyu; Song, Haixin; Rhee, Woogeun; Wang, Zhihua
• Is Part Of: Electronics letters. Volume 55:Issue 10(2019)
• Page Start: 585
• Page End: 587
• Publication Date: 2019-05-01
• Subjects: transient response -- voltage regulators -- CMOS integrated circuits -- analogue‐digital conversion; flash ADC‐based digital LDO -- nonlinear decoder -- exponential‐ratio array -- low‐dropout regulator -- flash ADC‐based parallel comparison -- power switch array -- high load driving capacity -- transient response -- CMOS integrated circuit -- voltage 1.0 V -- voltage 0.9 V -- time 6.0 mus -- current 48.0 mA -- frequency 1.0 MHz -- current 0.04 mA to 82.7 mA -- size 65 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2019.0505
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : This Letter presents a digital low‐dropout regulator (LDO) that achieves fast transient response with a flash ADC‐based parallel comparison. A non‐linear decoder is employed in the flash ADC to further enhance the transient response. In the design of the power switch array, an exponential‐ratio array (ERA) is adopted for high load driving capacity. The proposed digital LDO implemented in 65‐nm CMOS achieves a load range of 0.04–82.7 mA when the input voltage and the output voltage are 1.0 and 0.9 V, respectively. The digital LDO achieves a settling time of 6 μs with a load step of 48 mA, exhibiting the state‐of‐the‐art normalised settling time for the clock frequency of 1 MHz.