Yield modelling and analysis of bundled data and ring‐oscillator based designs. Issue 3 (5th April 2019)

• Record Type: Journal Article
• Authors: Zhang, Yang; Li, Ji; Cheng, Huimei; Zha, Haipeng; Draper, Jeffrey; Beerel, Peter A.
• Is Part Of: IET computers & digital techniques. Volume 13:Issue 3(2019)
• Page Start: 262
• Page End: 272
• Publication Date: 2019-04-05
• Subjects: Monte Carlo methods -- integrated circuit design -- integrated circuit testing -- clocks -- integrated circuit yield -- combinational circuits -- mathematical analysis -- logic gates -- delay lines; delay line -- Monte Carlo analysis -- bundled data -- ring‐oscillator -- bundled‐data designs -- shipped product quality -- process‐voltage‐temperature variations -- OR‐based clocks -- mathematical analysis -- combinational logic -- OR‐based circuits -- size 65.0 nm; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5040
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : The ill effects of process, voltage, and temperature variations are significantly reduced by ring‐oscillator (OR)‐based clocks and bundled‐data (BD) designs. Such designs include delay lines that enable the addition of test margin that can either by set uniformly across all manufactured chips or tuned individually per‐chip. This study mathematically analyses the resulting yield subject to a limit on shipped product quality providing a practical mechanism of optimising the test margins for these circuits. The model also provides a means of quantifying the benefits from the correlation in the delay line and combinational logic. In particular, using correlation values obtained from Monte Carlo analysis of a sample circuit in a 65 nm process, the model shows that BD and OR‐based circuits can have an over 50% yield advantage over their synchronous counterparts.