Two‐port–two‐port SI between RS485 and Ethernet with an FIFO queue for efficient PC‐to‐PC communication. Issue 3 (1st May 2020)

• Record Type: Journal Article
• Authors: Sung, Guo‐Ming; Shen, Yen‐Shih; Yu, Chih‐Ping; Jian, Cheng‐Syuan
• Is Part Of: IET networks. Volume 9:Issue 3(2020)
• Page Start: 102
• Page End: 109
• Publication Date: 2020-05-01
• Subjects: application specific integrated circuits -- local area networks -- computer network management; maximum Ethernet packet length -- data transfer rate -- total FIFO queue -- PC‐to‐PC communication -- two‐port Ethernet -- two‐port RS485 network serial interface -- packet transformation -- computer‐to‐computer communication -- transmitter manager -- receiver manager -- manager first‐in–first‐out queue -- data transmission rate -- application‐specific integrated circuit -- two‐port–two‐port SI -- time 139.31 mus -- voltage 1.8 V -- frequency 125 MHz -- frequency 115200 Hz -- bit rate 1 Gbit/s -- power 137 mW -- memory size 10 KByte -- bit rate 7.342 Mbit/s -- bit rate 7.5067 Mbit/s; Computer network architectures -- Periodicals; Computer network protocols -- Periodicals; Information networks -- Periodicals; Telecommunication systems -- Periodicals; 004.605
• DOI: 10.1049/iet-net.2019.0135
• Languages: English
• ISSNs: 2047-4954

Abstract

Abstract : This study proposes a two‐port Ethernet and two‐port RS485 network serial interface (SI) for packet transformation and data transmission for computer‐to‐computer communication. The proposed SI, which is composed of an RS485 module, an Ethernet module, a transmitter manager, a receiver manager, and the manager first‐in–first‐out (FIFO) queue, not only increases the data transmission rate but also guarantees correct communication between two Ethernet modules and two RS485 modules. An application‐specific integrated circuit is proposed to increase the operation frequency of the two‐port–two‐port SI. Furthermore, the large FIFO size enables the transmission of the maximum Ethernet packet length of 88 B and allows the latency of 51 clocks to be overcome. The measurement results indicate that the operating frequency, baud rate, data transfer rate, power consumption, processing delay, gate count, and chip size are 125 MHz, 115, 200 Hz, 1 Gbps, 137 mW, 139.31 µs, 162, 300, and 1.27 × 1.27 mm 2, respectively, at a power supply of 1.8 V and total FIFO queue of 10 kB. The error between the theoretical throughput (7.342 Mbps) and the measured throughput (7.5067 Mbps) was ∼2.24%.