0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology. Issue 7 (22nd October 2020)

• Record Type: Journal Article
• Authors: Kumar, Dhirendra; Anand, Rahul; Singh, Sajai Vir; Misra, Prasanna Kumar; Srivastava, Ashok; Goswami, Manish
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 7(2020)
• Page Start: 1001
• Page End: 1011
• Publication Date: 2020-10-22
• Subjects: oscillators -- random number generation -- statistical testing -- logic gates -- logic design -- CMOS logic circuits -- frequency dividers -- timing jitter; true random number generator -- jitter metastability -- current starved topology -- current starved inverter -- high‐frequency divider block -- jitter extraction -- metastable block -- sampling blocks -- post‐layout simulation -- power dissipation -- generated random numbers -- generated random signals -- TRNG design -- CMOS technology environment -- ring oscillator -- Cadence Virtuoso tool -- speed dissipation -- parametric analysis -- binary format -- Matlab -- NIST 800.22 statistical test suite -- Kolmogorov–Smirnov test -- Chi‐square test -- power 0.4 mW -- size 180.0 nm -- bit rate 1.5 Gbit/s; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0318
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter‐based ring oscillator (RO) with a high‐frequency divider block (designed by T‐FF followed by D‐FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The design avails fewer amenities to yield the reduction in hardware and enhances the degree of randomness. The post‐layout simulation of the proposed work was performed using a 180 nm CMOS technology environment in the Cadence Virtuoso tool. The speed and power dissipation achieved are 1.5 Gbps and 0.4 mW, respectively, with an efficiency of 0.27 pJ/bit. The effect of temperature and variation in supply voltages (by 10% around its nominal value) is also investigated on the generated random numbers through parametric analysis. For validation of randomness, the generated random signals are first sampled and then converted in binary format using MATLAB and finally verified by Kolmogorov–Smirnov and Chi‐square test for the uniformity and independency. The validity of the proposed work is done by NIST 800.22 statistical test suite. The proposed TRNG design achieved a very high‐pass efficiency.