Three‐dimensional AND flash memory. Issue 11 (11th May 2017)

• Record Type: Journal Article
• Authors: Kim, Y.; Park, I.H.; Kwon, H.T.; Wee, D.; Park, B.‐G.
• Is Part Of: Electronics letters. Volume 53:Issue 11(2017)
• Page Start: 739
• Page End: 741
• Publication Date: 2017-05-11
• Subjects: flash memories -- integrated circuit reliability -- parallel memories; 3D stacked vertical‐AND array -- parallel connected cell array structure -- bit‐sensing speed -- back‐pattern dependency -- word‐lines -- read current drivability -- threshold voltage window -- uniform program‐erase characteristics -- endurance cycle reliability -- high‐speed charge‐trapping AND flash memory array -- high‐density charge‐trapping AND flash memory array -- three‐dimensional AND flash memory; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2017.0465
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : High‐density and high‐speed charge‐trapping AND flash memory array is fabricated for the first time. A reliability of 10 4 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word‐lines, immunity to back‐pattern dependency, and fast bit‐sensing speed based on a parallel connected cell array structure, which are highly appropriate for three‐dimensional (3D) stacking. Finally, a novel 3D stacked vertical‐AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.