Switchable cache: utilising dark silicon for application specific cache optimisations. Issue 4 (1st July 2016)

• Record Type: Journal Article
• Authors: Nawinne, Isuru; Javaid, Haris; Ragel, Roshan; Parameswaran, Sri
• Is Part Of: IET computers & digital techniques. Volume 10:Issue 4(2016)
• Page Start: 157
• Page End: 164
• Publication Date: 2016-07-01
• Subjects: cache storage -- optimisation -- power aware computing -- transistors; switchable cache -- dark silicon -- application specific cache optimisations -- memory access time -- energy consumption -- cache configuration -- memory access patterns -- multiple cache configurations -- transistors -- exploration methodology; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2015.0114
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Caches are used to improve memory access time and energy consumption. The cache configuration which enables the best performance often differs between applications due to diverse memory access patterns. The authors present a new concept, called switchable cache, where multiple cache configurations exist on chip, leveraging the abundant transistors available due to what is known as the dark silicon phenomenon. Only one cache configuration is active at any given time based on the application under execution, while all other configurations remain inactive (dark). They describe an architecture to enable seamless integration of multiple cache configurations, and a novel design space exploration methodology to rapidly pre‐determine the optimal set of configurations at design‐time, for a given group of applications. For design spaces containing trillions of design points, the authors' exploration methodology always found the optimal solution in less than 2 s. The switchable cache improved memory access time by up to 26.2% when compared to a fixed cache.