Built‐in fast gather control network for efficient support of coherence protocols. Issue 2 (1st March 2013)

• Record Type: Journal Article
• Authors: Lodde, Mario; Roca, Toni; Flich, José
• Is Part Of: IET computers & digital techniques. Volume 7:Issue 2(2013)
• Page Start: 69
• Page End: 80
• Publication Date: 2013-03-01
• Subjects: microprocessor chips -- network‐on‐chip -- protocols -- shared memory systems; built‐in fast gather control network -- coherence protocols -- chip multiprocessors -- tile based design pattern -- on‐chip network -- NoC -- memory controllers -- communicating processors -- shared memory programming model -- coherence protocol -- memory hierarchy -- network control messaging -- Hammer protocol; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2012.0056
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Future chip multiprocessors will include hundreds of cores organised in a tile‐based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually an invalidation‐based protocol is used, where shared copies are invalidated before a write operation. In this study, the authors propose a NoC re‐organisation in which a small and fast dedicated control network is used to transmit acknowledgement messages related to the invalidation process, thus relieving the NoC from a considerable percentage of traffic. The dedicated control network is evaluated both with full map directories and with a broadcast‐based protocol (Hammer). Experimental evaluation shows significant gains in performance. With a low area overhead (<2.5%), the control network reduces NoC traffic and miss latency, thus reducing execution time up to 16%. Simulation results show a reduction of network traffic up to 80% and a reduction of store and load miss latency up to 70 and 40%, respectively.