A New Squarer design with reduced area and delay. Issue 5 (1st September 2016)
- Record Type:
- Journal Article
- Title:
- A New Squarer design with reduced area and delay. Issue 5 (1st September 2016)
- Main Title:
- A New Squarer design with reduced area and delay
- Authors:
- Banerjee, Arindam
Das, Debesh Kumar - Abstract:
- Abstract : Digital multiplier and squarer circuits are indispensable in digital signal processing and cryptography. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage that we can avoid the generation of many partial products by eliminating the redundant bits, thus resulting the circuit to be simpler with less amount of hardware, propagation delay and power consumption. Our work proposes an efficient algorithm using literals minimisation technique to achieve squaring with improved performance with respect to area, delay and power. This technique compares favourably with the recent work by offering less gate delay, transistor count and area. The proposed optimisation algorithm has been verified using different Xilinx and Altera Field Programmable Gate Array device family. Simulation results show better performance of our technique than the work shown in the past work in respect of delay, power and area. Moreover the proposed technique has been compared with the well known Radix‐4 Booth encoded squarer technique. Further, application specific integrated circuit (ASIC) implementation has been performed and the performance parameters have been compared with the earlier work and that also establishes the better results for our technique.
- Is Part Of:
- IET computers & digital techniques. Volume 10:Issue 5(2016)
- Journal:
- IET computers & digital techniques
- Issue:
- Volume 10:Issue 5(2016)
- Issue Display:
- Volume 10, Issue 5 (2016)
- Year:
- 2016
- Volume:
- 10
- Issue:
- 5
- Issue Sort Value:
- 2016-0010-0005-0000
- Page Start:
- 205
- Page End:
- 214
- Publication Date:
- 2016-09-01
- Subjects:
- digital arithmetic -- logic design
squarer design -- multiplier circuit -- squarer circuit -- digital signal processing -- cryptography -- literals minimisation technique -- Radix‐4 Booth encoded squarer technique
Computers -- Periodicals
Digital electronics -- Periodicals
Computer engineering -- Periodicals
Computer architecture -- Periodicals
Computer organization -- Periodicals
621.39 - Journal URLs:
- http://digital-library.theiet.org/content/journals/iet-cdt ↗
http://ieeexplore.ieee.org/servlet/opac?punumber=4117424 ↗
http://www.ietdl.org/IET-CDT ↗
https://ietresearch.onlinelibrary.wiley.com/journal/1751861x ↗
http://www.theiet.org/ ↗ - DOI:
- 10.1049/iet-cdt.2015.0170 ↗
- Languages:
- English
- ISSNs:
- 1751-8601
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 4363.252300
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 17389.xml