PSN‐aware circuit test timing prediction using machine learning. Issue 2 (25th January 2017)

• Record Type: Journal Article
• Authors: Liu, Yu‐Cheng; Han, Cheng‐Yu; Lin, Shih‐Yao; Li, James Chien‐Mo
• Is Part Of: IET computers & digital techniques. Volume 11:Issue 2(2017)
• Page Start: 60
• Page End: 67
• Publication Date: 2017-01-25
• Subjects: learning (artificial intelligence) -- circuit simulation -- VLSI -- integrated circuit testing -- integrated circuit noise -- neural nets -- regression analysis -- support vector machines -- feature extraction -- least squares approximations -- data reduction; PSN‐aware circuit test timing prediction -- machine learning -- power supply noise -- PSN -- IR drop -- yield loss -- very large scale integration chip testing -- circuit timing simulation -- neural network -- support vector regression -- SVR -- least‐square boosting -- LSBoost -- raw data dimension reduction -- feature extractions -- input‐output transition -- flip‐flop transition in window -- FFTW -- terminal FF transition of long paths -- switching activity in window -- SAW -- PATH -- physical‐aware features -- timing‐aware feature -- leon3mp benchmark circuit -- IOT method -- circuit simulation tools; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2016.0032
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Excessive power supply noise (PSN) such as IR drop can cause yield loss when testing very large scale integration chips. However, simulation of circuit timing with PSN is not an easy task. In this study, the authors predict circuit timing for all test patterns using three machine learning techniques, neural network (NN), support vector regression (SVR), and least‐square boosting (LSBoost). To reduce the huge dimension of raw data, they propose four feature extractions: input/output transition (IOT), flip‐flop transition in window (FFTW), switching activity in window (SAW), and terminal FF transition of long paths (PATH). SAW and FFTW are physical‐aware features while PATH is a timing‐aware feature. Their experimental results on leon3mp benchmark circuit (638 K gates, 2 K test patterns) show that, compared with the simple IOT method, SAW effectively reduced the dimension by up to 472 times, without significant impact on prediction accuracy [correlation coefficient = 0.79]. Their results show that NN has best prediction accuracy and SVR has the least under‐prediction. LSBoost uses the least memory. The proposed method is more than six orders of magnitude faster than traditional circuit simulation tools.