Impact of stress in ICP‐CVD SiNx passivation films on the leakage current in AlGaN/GaN HEMTs. Issue 15 (1st July 2018)

• Record Type: Journal Article
• Authors: Cho, S.‐J.; Li, X.; Guiney, I.; Floros, K.; Hemakumara, D.; Wallis, D.J.; Humphreys, C.; Thayne, I.G.
• Is Part Of: Electronics letters. Volume 54:Issue 15(2018)
• Page Start: 947
• Page End: 949
• Publication Date: 2018-07-01
• Subjects: leakage currents -- aluminium compounds -- gallium compounds -- III‐V semiconductors -- wide band gap semiconductors -- high electron mobility transistors -- silicon compounds -- passivation -- stress analysis -- plasma CVD; stress impact -- ICP‐CVD passivation films -- HEMTs -- room temperature inductively coupled plasma chemical vapour deposited surface passivation layers -- off‐state drain -- SiNx -- temperature 293 K to 298 K -- size 2 mum -- strain engineered surface passivation approach -- subthreshold slope -- compressively stressed bilayer passivation scheme -- high electron mobility transistors -- gate leakage currents; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2018.1097
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : The impact of the stress in room temperature inductively coupled plasma chemical vapour deposited (ICP‐CVD) SiN x surface passivation layers on off‐state drain ( I DS‐off ) and gate leakage currents ( I GS ) in AlGaN/GaN high electron mobility transistors (HEMTs) is reported. I DS‐off and I GS in 2 μm gate length devices were reduced by up to four orders of magnitude to ∼10 pA/mm using a compressively stressed bilayer SiN x passivation scheme. In addition, I on / I off of ∼10 11 and subthreshold slope of 68 mV/dec were obtained using this strain engineered surface passivation approach.