A 2.67 fJ/c.‐s. 27.8 kS/s 0.35 V 10‐bit successive approximation register analogue‐to‐digital converter in 65 nm complementary metal oxide semiconductor. Issue 6 (1st November 2014)

• Record Type: Journal Article
• Authors: Zhu, Zhangming; Qiu, Zheng; Shen, Yi; Yang, Yintang
• Is Part Of: IET circuits, devices & systems. Volume 8:Issue 6(2014)
• Page Start: 427
• Page End: 434
• Publication Date: 2014-11-01
• Subjects: analogue-digital conversion -- flip-flops -- CMOS logic circuits -- comparators (circuits); successive approximation register analogue-to-digital converter -- complementary metal oxide semiconductor -- ultralow-power SAR ADC design -- nanowatt range power consumption -- segmented-capacitor array structure -- ultralow-voltage design -- ultralow-voltage operation -- bulk-driven-based fully-dynamic comparator -- latched dynamic logic cell -- decision error elimination -- boosting technique -- digital-to-analogue converter driving switch -- double-boosted sample switch -- leakage current reduction -- sampling linearity -- signal-to-noise distortion ratio -- figure-of-merit -- voltage 0.35 V -- size 65 nm -- power 25.2 nW -- word length 10 bit; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2013.0446
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : A design of a 10‐bit 27.8 kS/s 0.35 V ultra‐low power successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. Nano‐watt range power consumption is achieved thanks to the proposed segmented‐capacitor array structure and ultra‐low voltage design. To facilitate ultra‐low voltage operation, a bulk‐driven based fully dynamic comparator is proposed. A novel latched dynamic logic cell is introduced to eliminate decision error caused by leakage current. Boosting technique is introduced in digital‐to‐analogue converter (DAC) driving switch to relieve non‐linearity. A new double‐boosted sample switch is employed to reduce leakage current and improve sampling linearity. The ADC was fabricated in 65 nm complementary metal oxide semiconductor. Drawing 25.2 nW from a single 350 mV supply, the ADC achieves 52.14 dB signal‐to‐noise distortion ratio and 8.4‐bit effective number of bits resulting in a figure‐of‐merit of 2.67 fJ/conversion‐step.