DHL‐cache: dynamic per history length adjustment for low‐power L2 cache. Issue 15 (1st July 2016)

• Record Type: Journal Article
• Authors: Joo, H.W.; Chung, E.Y.
• Is Part Of: Electronics letters. Volume 52:Issue 15(2016)
• Page Start: 1297
• Page End: 1298
• Publication Date: 2016-07-01
• Subjects: low‐power electronics -- microprocessor chips -- cache storage -- content‐addressable storage; DHL‐cache -- low‐power L2 cache -- power dissipation -- on‐chip L2 cache -- microprocessors -- high‐associative large‐L2 cache -- fragmented locality -- L1 cache -- dynamic per history length adjustment cache -- way‐prediction window size -- access history pattern -- way‐prediction accuracy -- energy‐delay product improvement -- minimum hardware support; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2016.1465
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : The significant power dissipation of the on‐chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low‐power technique for a high‐associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL‐cache) dynamically selects the qualified way candidates to be accessed and controls the way‐prediction window size based on the access history pattern. With a high degree of the way‐prediction accuracy, the DHL‐cache shows a 55.3% energy‐delay product improvement over the location‐cache with minimum hardware support. Therefore, the DHL‐cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.