23 × 12 μm three‐stage amplifier using sub‐threshold active cascode compensation capable of driving very‐large‐load with no‐upper‐limit. Issue 16 (1st August 2019)

• Record Type: Journal Article
• Authors: Yan, Zhanke; Zhang, Chunming; Wang, Menghai; Chen, Haifeng
• Is Part Of: Electronics letters. Volume 55:Issue 16(2019)
• Page Start: 881
• Page End: 883
• Publication Date: 2019-08-01
• Subjects: CMOS analogue integrated circuits -- amplifiers -- active networks -- transient response -- integrated circuit design; ultra‐large capacitive loads -- large‐signal transient response -- CMOS technology -- three‐stage amplifier -- slew‐rate -- sub‐threshold active cascode -- power 16.5 muW -- voltage 1.05 V -- capacitance 40.0 fF; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2019.1983
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : An ultra‐area‐efficient three‐stage amplifier is proposed by using sub‐threshold active cascade compensation, which is able to drive very‐large or ultra‐large capacitive loads without sacrificing stability and power. Besides, external feed‐forward path and slew‐rate enhancer can significantly improve the large‐signal transient response of the circuit. Designed and verified in 28 nm CMOS technology, the proposed amplifier occupies die area of 0.00028 mm 2 and consumes a power of 16.5 µW from 1.05 V supply. In addition, it can provide over 85 dB DC gain and is stable for any load larger than 4 nF, while the size of the entailed compensation capacitance is only 40 fF.