Energy‐efficient LDPC codec design using cost‐effective early termination scheme. Issue 2 (19th December 2018)

• Record Type: Journal Article
• Authors: Lin, Cheng‐Hung; Wu, Yuan‐Syun; Song, Chen‐Pei
• Is Part Of: IET computers & digital techniques. Volume 13:Issue 2(2019)
• Page Start: 118
• Page End: 125
• Publication Date: 2018-12-19
• Subjects: codecs -- decoding -- parity check codes -- CMOS integrated circuits -- cyclic codes -- iterative decoding; energy‐efficient LDPC codec design -- cost‐effective early termination scheme -- energy‐efficient codec design -- decoding iterations -- ET scheme -- QC‐LDPC codec -- decoding energy efficiency -- energy reduction -- quasicyclic‐low‐density parity‐check code -- TSMC CMOS technology -- QC‐LDPC code -- size 90.0 nm -- frequency 278.0 MHz -- size 9.86 mm -- bit rate 4.3 Gbit/s -- bit rate 4.4 Gbit/s; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5074
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Here, the authors propose an energy‐efficient codec design using a rate‐0.91 systematic quasi‐cyclic‐low‐density parity‐check (QC‐LDPC) code. A cost‐effective early termination (ET) scheme is presented for efficiently terminating the decoding iterations and maintaining desirable correcting performance. Compared with no ET scheme, the cost‐effective ET scheme achieves 54.6% energy reduction with 1.7% area overhead. Finally, the proposed QC‐LDPC codec employing the cost‐effective ET scheme is implemented in a prototyping chip of 9.86 mm 2 core area using the TSMC 90 nm CMOS technology. Compared with the other decoder chips, the prototyping codec operating at 278 MHz achieves the best decoding energy efficiency of 156 pJ/bit with a high decoding throughput of 4.3 Gbps. The prototyping codec also achieves a high encoding throughput of 4.4 Gbps.