Digital bilinear feedback for low‐power double‐sampling sigma–delta modulators. Issue 1 (1st January 2015)

• Record Type: Journal Article
• Authors: De Bock, M.; Rombouts, P.
• Is Part Of: Electronics letters. Volume 51:Issue 1(2015)
• Page Start: 27
• Page End: 29
• Publication Date: 2015-01-01
• Subjects: digital filters -- low‐power electronics -- sigma‐delta modulation -- circuit feedback -- interference suppression -- circuit noise -- power consumption; digital bilinear feedback -- low‐power double‐sampling sigma‐delta modulators -- digital bilinear filter -- feedback path -- modulator loop -- quantisation noise folding suppression -- QNF -- double‐sampling path mismatch -- input sampling capacitor -- feedback sampling capacitor -- power consumption -- input signal buffer -- single‐ended circuit; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2014.3016
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A novel double‐sampling (DS) technique for use in sigma–delta modulators (ΣΔMs) is presented. The proposed technique uses a digital bilinear filter in the feedback path of the modulator loop. The bilinear filter suppresses the quantisation noise folding (QNF) that results from the DS path mismatch. Unlike other solutions for the QNF, the digital implementation of this filter allows the sharing of the input sampling capacitor with the feedback sampling capacitor without any additional analogue gain stages. This way, the power consumption in the input signal buffer can be greatly reduced, because it benefits from the nullator effect at the input of the ΣΔM loop, and hence the current needed to drive the shared sampling capacitor is drastically reduced. Moreover, the proposed DS technique is also suitable for a single‐ended circuit implementation of DS.