An asynchronous mesh NoC based booth multiplication. Issue 1 (5th September 2018)

• Record Type: Journal Article
• Authors: He, Anping; Feng, Guangbo; Jilin, Zhang; Wu, Jinzhao
• Is Part Of: IET circuits, devices & systems. Volume 13:Issue 1(2019)
• Page Start: 73
• Page End: 78
• Publication Date: 2018-09-05
• Subjects: integrated logic circuits -- digital arithmetic -- field programmable gate arrays -- asynchronous circuits -- logic design -- multiplying circuits -- network-on-chip; asynchronous mechanism -- 8-bit asynchronous Booth multiplier -- asynchronous mesh -- IC system -- asynchronous control -- Booth algorithm -- arithmetic units -- Xilinx Virtex-7 FPGA; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.0058
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : The multiplier is one of the most important arithmetic units, which is an essential part of an IC system and affects its efficiency dramatically. The Booth structure of a multiplier is a wide‐used and efficient structure of real IC systems, and the performance of a Booth multiplier would be mainly determined by partial product issues, e.g., multiplication and addition, as well as the frequency of the clock. Then, one of the potential improvements would be the asynchronous control to reduce power by cancelling the global clock, the other be the structure and implementation of the algorithm for high performance, and the last could be the benefits of reconfiguration for sharing process elements. In this paper, we proposed a Booth algorithm which organized by an asynchronous NoC, e.g., the partial product generators are located into a configurable network, and other part of the circuit are organized and adjusted by an asynchronous mechanism. The design is finally implemented by an 8‐bit asynchronous Booth multiplier, which is synthesized and post simulated with a Xilinx Virtex‐7 FPGA development board.