Implementation of MIMO data reordering and scheduling methodologies for eight‐parallel variable length multi‐path delay commutator FFT/IFFT. Issue 5 (1st September 2016)

• Record Type: Journal Article
• Authors: Locharla, Govinda Rao; Kallur, Sudeendra Kumar; Mahapatra, Kamala Kanta; Ari, Samit
• Is Part Of: IET computers & digital techniques. Volume 10:Issue 5(2016)
• Page Start: 215
• Page End: 225
• Publication Date: 2016-09-01
• Subjects: scheduling -- fast Fourier transforms -- inverse transforms -- wireless LAN -- OFDM modulation -- MIS devices -- clocks -- power aware computing -- MIMO communication; MIMO data reordering -- scheduling methodology -- eight‐parallel variable length multipath delay commutator -- fifth generation wireless fidelity technology -- multiuser multiple‐input multiple‐output orthogonal frequency division multiplexing technique -- MU MIMO‐OFDM technique -- data rate communication -- physical layer design -- high data rate wireless systems -- OFDM modulation -- forward‐inverse fast Fourier transform processor -- pipelined FFT‐IFFT processor -- multipath delay commutator‐based FFT‐IFFT processor -- IEEE 802.11ac compliant MU MIMO‐OFDM system -- clock gating -- TSMC complementary metal‐oxide‐semiconductor technology -- clock gated implementation; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2015.0165
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : The IEEE 802.11ac is the recently ratified standard developed for the fifth generation wireless fidelity technology, in which the multi‐user (MU) multiple‐input multiple‐output orthogonal frequency division multiplexing (MIMO‐OFDM) technique is adopted for the high data rate communication. In an MIMO‐OFDM System, the forward/inverse fast Fourier transform (FFT/IFFT) processor is a key component. On proper reception, the reordering and scheduling of data is important for the optimal utilisation of butterfly resources in the pipelined FFT/IFFT processor. In this study, a mathematical model for an eight‐parallel multimode ( N = 512/256/128/64) multi‐path delay commutator‐based FFT/IFFT processor which is suitable for the IEEE 802.11ac compliant MU‐MIMO‐OFDM system is presented. On the other hand, the data reordering, scheduling methodologies and its architectures are proposed for the pre‐, post‐FFT/IFFT process are proposed. The design implementations are done using TSMC 65 nm complementary metal–oxide–semiconductor technology at 160 MHz. The power and area metrics with and without clock gating are compared. The clock gated implementation reports show that the power consumption is 17.44 mW for the pre‐transformed data reordering and 11.64 mW for the post‐transformed data reordering with an area occupation of 0.7694 mm 2 and 0.5111 mm 2, respectively.