Tiny – optimised 3D mesh NoC for area and latency minimisation. Issue 3 (1st January 2014)

• Record Type: Journal Article
• Authors: Marcon, C.; Webber, T.; Fernandes, R.; Cataldo, R.; Grando, F.; Poehls, L.; Benso, A.
• Is Part Of: Electronics letters. Volume 50:Issue 3(2014)
• Page Start: 165
• Page End: 166
• Publication Date: 2014-01-01
• Subjects: integrated circuit design -- network‐on‐chip; Tiny‐optimised 3D mesh NoC -- latency minimisation -- scalable 3D NoC design -- efficient three‐dimensional network‐on‐chip design -- area reduction -- theoretical analysis -- basic 3D mesh NoC -- injection rates -- traffic mapping; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2013.2557
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Tiny is a scalable and efficient three‐dimensional (3D) network‐on‐chip (NoC) designed to reduce latency and area. A theoretical analysis demonstrates its efficiency when compared with a basic 3D mesh NoC. Mapping independent traffics with different injection rates makes the trade‐offs analysis of Tiny possible. Results highlight that Tiny always reduces area and for several cases minimises latency.