Design of multiplierless prototype filter for two‐channel filter bank using hybrid method in FCSD space. Issue 1 (1st January 2017)

• Record Type: Journal Article
• Authors: Sharma, Ila; Kumar, Anil; Singh, Girish Kumar; Lee, Heung‐No
• Is Part Of: IET circuits, devices & systems. Volume 11:Issue 1(2017)
• Page Start: 29
• Page End: 40
• Publication Date: 2017-01-01
• Subjects: channel bank filters -- particle swarm optimisation -- ant colony optimisation -- circuit optimisation; multiplierless prototype filter design -- FCSD space -- hybrid method-based design -- multiplierless two-channel filter bank -- stopband attenuation -- roll-off factor -- canonical sign digit space -- factorised canonical sign digit space -- particle swarm optimisation -- artificial bee colony algorithm -- quantised filter coefficients -- target field programmable gate arrays XC3S500E-4-FG320 -- Xilinx Spartan 3E starter board -- windowing method; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2016.0124
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : In this work, a hybrid method‐based design of multiplierless two‐channel filter bank has been proposed with a given stopband attenuation ( A s ) and roll‐off factor. Windowing method has been used for efficient design of a prototype filter with novelty of exploiting quantised coefficients in canonical sign digit (CSD) and factorised canonical sign digit (FCSD) space by merging the concept of particle swarm optimisation and artificial bee colony algorithm. The quantised filter coefficients are optimised by varying cut‐off frequency such that the magnitude response of prototype filter is approximately reduced to 0.707 at quadrature frequency. The implemented filter is synthesised using target field programmable gate arrays XC3S500E‐4‐FG320 on Xilinx Spartan 3E starter board. The performances of designed prototype filter is compared with the earlier published works in terms of reconstruction error, amplitude distortion, slices, flip‐flops, four‐input lookup tables and adders. The synthesis results demonstrate that the significant reduction in hardware is achieved in term of adder gain. For filter order, N = 32, and word length 12, the adder gain achieved in CSD and FCSD is 41.77 and 43.07%, respectively, while for N = 30, it is 35.44% in CSD and 36.70% in FCSD, respectively.