0.65 V integrable electronic realisation of integer‐ and fractional‐order Hindmarsh–Rose neuron model using companding technique. Issue 6 (29th October 2018)

• Record Type: Journal Article
• Authors: Khanday, Farooq Ahmad; Dar, Mohammad Rafiq; Kant, Nasir Ali; Rossello, Josep L.; Psychalinos, Costas
• Is Part Of: IET circuits, devices & systems. Volume 12:Issue 6(2018)
• Page Start: 696
• Page End: 706
• Publication Date: 2018-10-29
• Subjects: integrated circuit design -- CMOS integrated circuits -- synchronisation -- integrated circuit modelling -- neural chips -- low-power electronics -- MOSFET circuits; integrator -- fractional-order Hindmarsh–Rose neuron model -- sinh companding technique -- HR neuron model -- integer-order models -- neocortical pyramidal neurons -- multiple time-scales -- fractional-order differentiation -- differentiator -- integrable electronic realisation -- external excitation -- HR neuron models -- MOS transistors -- grounded capacitors -- electronic tunability -- complementary metal–oxide–semiconductor technology process -- HSPICE simulation software -- firing rate -- voltage 0.65 V -- size 130.0 nm; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2018.5033
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : Some neurons like neocortical pyramidal neurons adapt with multiple time‐scales, which is consistent with fractional‐order differentiation. The fractional‐order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer‐order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer‐ and fractional‐order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low‐voltage and low‐power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal‐oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional‐order and integer‐order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software.