8.4‐to‐16‐bit resolution, 1‐to‐16 kHz bandwidth ADC with programmable‐gain functionality for multi‐sensor applications. Issue 18 (1st September 2019)

• Record Type: Journal Article
• Authors: Rhee, C.; Kim, S.
• Is Part Of: Electronics letters. Volume 55:Issue 18(2019)
• Page Start: 982
• Page End: 984
• Publication Date: 2019-09-01
• Subjects: CMOS integrated circuits -- analogue‐digital conversion -- low‐power electronics -- delta‐sigma modulation -- sensor fusion -- modulators; multisensor system -- bio‐signals -- PG NS SAR ADC -- third‐order delta‐sigma modulator -- programmable‐gain first‐order noise‐shaping SAR ADC -- PG first‐order NS successive‐approximation register analogue‐to‐digital converter -- voltage 1.8 V; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2019.1496
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A resolution‐reconfigurable, bandwidth‐scalable analogue‐to‐digital converter (ADC) with programmable‐gain (PG) functionality for a multi‐sensor system, which encompasses various signals such as bio‐signals and battery‐level, is presented. In PG and low‐power mode, a PG first‐order noise‐shaping (NS) successive‐approximation register (SAR) ADC achieves 8.4‐to‐10.2‐bit operating up to 16 kHz while providing a gain of 1/2/4. The PG NS SAR ADC can be reconfigured as an adder and a quantiser in a delta‐sigma (ΔΣ) modulator enhancing the order of the modulator for high‐resolution. The third‐order ΔΣ modulator achieves 16.1 bits in a bandwidth of 1 kHz. The work is implemented in a 0.18 μm CMOS process with a 1.8 V power supply.