0.0012 mm2, 8 mW, single‐to‐differential converter with < 1.1% data cross error and < 3.4 ps RMS jitter up to 14 Gbit/s data rate. Issue 11 (1st May 2013) - Chen, Yong; Mak, Pui‐In; Zhang, Li; Qian, He; Wang, Yan
Abstract : An extremely compact, doubly balancing single‐to‐differential converter (S2D) for high‐speed wireline systems is reported. It incorporates a two‐stage topology with 'coarse balancing' in the first stage and 'fine balancing' in the second stage by adopting a compact 'positive‐feedback active inductor' that simultaneously boosts the signal bandwidth. Fabricated in 65 nm CMOS, the S2D measures < 1.1% data cross error and < 3.4 ps RMS jitter up to a 14 Gbit/s data rate. The die occupies 0.0012 mm 2 and consumes 8 mW.