A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge inverters. Issue 4 (16th February 2021)

• Record Type: Journal Article
• Authors: Mehta, Pavan; Sahoo, Subhanarayan; Kumar, Mayank
• Is Part Of: IET circuits, devices & systems. Volume 15:Issue 4(2021)
• Page Start: 366
• Page End: 376
• Publication Date: 2021-02-16
• Subjects: Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/cds2.12033
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract: Reliability is a major concern for multilevel inverters (MLIs) in all industrial applications. The consequences of faults increase as the number of power semiconductor devices increases and may lead to serious damage to the overall system. To prevent such issues, an effective fault‐detection technique is required. A detailed analysis is presented of five‐level cascaded H‐bridge MLIs under healthy and faulty conditions. A fault‐detection technique based on total harmonic distortion and a normalized output voltage factor is presented. Also discussed is a fault‐isolation technique based on reduction of amplitude modulation, which results in a fault‐tolerant inverter. The level‐shifted pulse‐width modulation (LSPWM) technique is used for switching operation. LSPWM is most suitable for MLIs that require less computational effort. The presented fault‐diagnosis technique can be implemented on MLI‐based drives, grid‐connected operations etc. without any major changes. The simulation and hardware results are presented to validate the proposed fault‐detection and fault‐tolerant control technique at different power factors.