Cite
HARVARD Citation
Pandey, C. et al. (2021). A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET. Microelectronics and reliability. p. . [Online].
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Pandey, C. et al. (2021). A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET. Microelectronics and reliability. p. . [Online].