Symmetric switched diode multilevel inverter structure with minimised switch count. Issue 8 (4th August 2017)

• Record Type: Journal Article
• Authors: Ibrahim, S.A. Ahamed; Palanimuthu, Anbalagan; Sathik, M.A. Jagabar
• Is Part Of: Journal of engineering. Volume 2017:Issue 8(2017)
• Page Start: 469
• Page End: 478
• Publication Date: 2017-08-04
• Subjects: invertors -- harmonic distortion -- harmonics suppression; high‐voltage applications -- hardware prototype model -- Matlab‐Simulink simulation software -- seven‐level output voltage simulation -- total power losses -- power diode -- insulated bipolar junction transistors -- total harmonic distortion reduction -- synthesised stepped output voltage waveform production -- double‐source units -- medium‐voltage applications -- power switch reduction -- switch count minimisation -- symmetric switched diode multilevel inverter structure; Engineering -- Periodicals; Engineering; Electronic journals; Periodicals; 620.005
• DOI: 10.1049/joe.2017.0174
• Languages: English
• ISSNs: 2051-3305

Abstract

Abstract : A new symmetric switched diode multilevel inverter with reduced power switches for medium‐voltage applications is presented. The proposed topology consists of several double‐source units to produce the synthesised stepped output voltage waveform with reduced total harmonic distortion. The required number of insulated bipolar junction transistors, power diode, and total power losses are compared between conventional and recent topologies. The seven‐level output voltage is simulated by using simulation software MATLAB/Simulink, and hardware prototype model has been developed to prove the superiority of the proposed topology. Finally, the advantage of the proposed topology is highlighted, and the topology for high‐voltage applications is suggested.