Capacitive digital‐to‐analogue converters with least significant bit down in differential successive approximation register ADCs. Issue 1 (30th January 2014)

• Record Type: Journal Article
• Authors: Sun, Lei; Pun, Kong‐Pang; Ng, Wai‐Tung
• Is Part Of: Journal of engineering. Volume 2014:Issue 1(2014)
• Page Start: 45
• Page End: 48
• Publication Date: 2014-01-30
• Subjects: analogue‐digital conversion -- digital‐analogue conversion -- logic circuits; capacitive digital‐to‐analogue converters -- differential successive approximation register ADC -- least signihcant bit‐down switching scheme -- CDAC -- unit capacitor -- chip area -- switching energy -- logic circuits -- DNL‐INL performance; Engineering -- Periodicals; Engineering; Electronic journals; Periodicals; 620.005
• DOI: 10.1049/joe.2013.0219
• Languages: English
• ISSNs: 2051-3305

Abstract

Abstract : This Letter proposes a least significant bit‐down switching scheme in the capacitive digital‐to‐analogue converters (CDACs) of successive approximation register analog‐to‐digital converter (ADC). Under the same unit capacitor, the chip area and the switching energy are halved without increasing the complexity of logic circuits. Compared with conventional CDAC, when it is applied to one of the most efficient switching schemes, V cm ‐based structure, it achieves 93% less switching energy and 75% less chip area with the same differential non linearity (DNL)/integral non linearity (INL) performance.