Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs. (7th October 2013)

• Record Type: Journal Article
• Authors: Moshgelani, Farid; Al-Khalili, Dhamin; Rozon, Côme
• Other Names: Sawan Mohamad Academic Editor.
• Is Part Of: Journal of electrical and computer engineering. Volume 2013(2013)
• Publication Date: 2013-10-07
• Subjects: Computer engineering -- Periodicals; Electrical engineering -- Periodicals; 621.3905
• DOI: 10.1155/2013/454392
• Languages: English
• ISSNs: 2090-0147

Abstract

Abstract : We are examining different configurations and circuit topologies for arithmetic components such as adder and compressor circuits using both symmetric and asymmetric work-function FinFETs. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50%, respectively, compared to results in the literature. For the 14-transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29%, respectively, compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achives reduction in leakage current by 85% with a small degradation of 7% in delay. The compressor circuits, using asymmetric devices for one of the proposed configurations, achieve reduction in both leakage current and delay by 86% and 4%, respectively. All simulations are based on a 25 nm FinFET technology using the University of Florida UFDG model.