Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections. (10th May 2012)

• Record Type: Journal Article
• Authors: Cong, Jason; Gururaj, Karthik; Zhang, Peng; Zou, Yi
• Other Names: Xie Yuan Academic Editor.
• Is Part Of: Journal of electrical and computer engineering. Volume 2012(2012)
• Publication Date: 2012-05-10
• Subjects: Computer engineering -- Periodicals; Electrical engineering -- Periodicals; 621.3905
• DOI: 10.1155/2012/691864
• Languages: English
• ISSNs: 2090-0147

Abstract

Abstract : The ever-increasing design complexity of modern digital systems makes it necessary to develop electronic system-level (ESL) methodologies with automation and optimization in the higher abstraction level. How the concurrency is modeled in the application specification plays a significant role in ESL design frameworks. The state-of-art concurrent specification models are not suitable for modeling task-level concurrent behavior for the hardware synthesis design flow. Based on the concurrent collection (CnC) model, which provides the maximum freedom of task rescheduling, we propose task-level data model (TLDM), targeted at the task-level optimization in hardware synthesis for data processing applications. Polyhedral models are embedded in TLDM for concise expression of task instances, array accesses, and dependencies. Examples are shown to illustrate the advantages of our TLDM specification compared to other widely used concurrency specifications.