H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. Issue 5 (1st September 2015)

• Record Type: Journal Article
• Authors: Belhadj, Nidhameddine; Bahri, Nejmeddine; Marrakchi, Zied; Ben Ayed, Mohamed Ali; Masmoudi, Nouri; Mehrez, Habib
• Is Part Of: IET computers & digital techniques. Volume 9:Issue 5(2015)
• Page Start: 259
• Page End: 267
• Publication Date: 2015-09-01
• Subjects: system‐on‐chip -- video coding -- multiprocessing systems -- field programmable gate arrays -- virtual prototyping -- electronic engineering computing; H.264/AVC high definition intracoding implementation -- multiprocessor system on chip technology architecture -- MPSoC architecture -- video encoders -- SoCLib -- open platform -- virtual prototyping -- central processing unit -- video reconstruction -- data loading latency constraint -- memory requirement -- FPGA technology -- virtual platform; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2014.0151
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Exploiting the multiprocessor system on chip technology (MPSoC) is a promising way to improve the frame rate of latest video encoders. In this article, an MPSoC architecture for the intra prediction encoding chain of H.264/AVC high definition is proposed using SoCLib, an open platform for virtual prototyping of MPSoC architectures. Experimental results show a speedup of about 85% in processing time, compared with an execution based on a single central processing unit, with an acceptable final circuit area. The proposed parallelism does not affect the quality of the reconstructed video and bit rate. It takes into account the data loading latency constraint and the size of used memory requirement. The proposed architecture is validated on FPGA technology, using a technique that allows switching from a virtual platform to a hardware one.