Unified multi‐objective mapping for network‐on‐chip using genetic‐based hyper‐heuristic algorithms. Issue 4 (15th March 2018)

• Record Type: Journal Article
• Authors: Xu, Changqing; Liu, Yi; Li, Peng; Yang, YinTang
• Is Part Of: IET computers & digital techniques. Volume 12:Issue 4(2018)
• Page Start: 158
• Page End: 166
• Publication Date: 2018-03-15
• Subjects: network‐on‐chip -- genetic algorithms; unified multiobjective mapping -- network‐on‐chip -- genetic‐based hyperheuristic algorithms -- energy‐aware mapping approach -- delay‐aware mapping approach -- energy consumption -- communication latency -- NoC -- GHA -- bottom‐level optimisation -- top‐level optimisation; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2017.0156
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : In this study, a flexible energy‐ and delay‐aware mapping approach is proposed for the co‐optimisation of energy consumption and communication latency for network‐on‐chips (NoCs). A novel genetic‐based hyper‐heuristic algorithm (GHA) is proposed as the core algorithm. This algorithm consists of bottom‐level optimisation which includes a variety of operators and top‐level optimisation which selects suitable operators through a 'reward' mechanism. As this algorithm can select suitable operators automatically during the mapping process, it noticeably improves convergence speed and demonstrates excellent stability. Compared to the random algorithm, GHA can achieve on average 23.28% delay reduction and 11.81% power reduction. Compared to state‐of‐the‐art mapping algorithms, GHA produces improved mapping results with less time, especially when the size of NoC is large.