Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g. Issue 5 (23rd April 2020)

• Record Type: Journal Article
• Authors: Kumar, Ganjikunta Ganesh; Sahoo, Subhendu K.
• Is Part Of: IET computers & digital techniques. Volume 14:Issue 5(2020)
• Page Start: 193
• Page End: 200
• Publication Date: 2020-04-23
• Subjects: OFDM modulation -- fast Fourier transforms -- field programmable gate arrays -- power consumption -- digital arithmetic -- CMOS logic circuits -- Zigbee; power‐efficient variable‐length fast Fourier transform -- MR‐OFDM physical layer -- IEEE 802.15.4‐g standard -- multirate orthogonal frequency division multiplexing physical layer -- multiregional orthogonal frequency division multiplexing physical layer -- mixed‐radix algorithm -- configurable complex constant multiplier structure -- W128 twiddle factor multiplication -- Altera field‐programmable gate array devices -- mixed‐radix FFT architecture -- variable‐length FFT architecture gate count -- post‐synthesis -- hardware cost reduction -- Xilinx Virtex‐5 -- 16‐32‐64‐128‐point single‐path delay feedback pipeline fast Fourier transform architecture -- W64 twiddle factor multiplication -- W32 twiddle factor multiplication -- hardware‐sharing mechanism -- memory space requirement reduction -- 128‐point FFT -- complementary metal‐oxide‐semiconductor technology -- power consumption -- area‐efficient variable‐length fast Fourier transform -- size 90.0 nm -- voltage 1.0 V -- power 3.832 mW -- word length 12 bit; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5260
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : The authors present a novel 16/32/64/128‐point single‐path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi‐rate and multi‐regional orthogonal frequency division multiplexing (MR‐OFDM) physical layer of IEEE 802.15.4‐g. The proposed FFT architecture employs a mixed‐radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W 32, W 64, and W 128 twiddle factor multiplication. A hardware‐sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128‐point FFT computation scheme. The proposed design is implemented in Xilinx Virtex‐5 and Altera's field‐programmable gate array devices. For the computation of 128‐point FFT, the proposed mixed‐radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal‐oxide‐semiconductor technology with a supply voltage of 1 V. Post‐synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable‐length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word‐length is 12‐bits and can be efficiently useful for the IEEE 802.15.4‐g standard.