Truncated ternary multipliers. Issue 2 (1st March 2015)

• Record Type: Journal Article
• Authors: Parhami, Behrooz
• Is Part Of: IET computers & digital techniques. Volume 9:Issue 2(2015)
• Page Start: 101
• Page End: 105
• Publication Date: 2015-03-01
• Subjects: digital arithmetic -- multiplying circuits; truncated ternary multipliers -- balanced ternary number representation -- symmetric radix‐3 digit set -- balanced ternary arithmetic -- representational symmetry -- favourable error characteristics -- truncation -- lower‐error truncated multiplication -- cost reduction -- truncated binary multiplier; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2013.0133
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Balanced ternary number representation and arithmetic, based on the symmetric radix‐3 digit set {−1, 0, +1}, has been studied at various times in the history of computing. Among established advantages of balanced ternary arithmetic are representational symmetry, favourable error characteristics and rounding by truncation. In this study, we show an additional advantage: that of lower‐error truncated multiplication with the same relative cost reduction as in truncated binary multipliers.