Write‐variation aware alternatives to replace SRAM buffers with non‐volatile buffers in on‐chip interconnects. Issue 6 (20th August 2019)

• Record Type: Journal Article
• Authors: Rani, Khushboo; Kapoor, Hemangee K.
• Is Part Of: IET computers & digital techniques. Volume 13:Issue 6(2019)
• Page Start: 481
• Page End: 492
• Publication Date: 2019-08-20
• Subjects: integrated circuit design -- network‐on‐chip -- buffer circuits -- CMOS memory circuits -- SRAM chips -- cache storage -- MRAM devices; SRAM buffers -- nonvolatile buffers -- on‐chip interconnects -- CMOS technology -- multiple processors -- network‐on‐chip -- NoC interconnects -- leakage power consumption -- NoC buffers -- nonvolatile spin transfer torque random access memory‐based buffers -- STT‐RAM technology -- write‐variations -- virtual channel allocation policies -- VC allocation policies -- iso‐area‐based alternatives -- pure STT‐RAM buffers -- SRAM technology -- write variation; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2019.0039
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : With the advancement in CMOS technology and multiple processors on the chip, communication across these cores is managed by a network‐on‐chip (NoC). Power and performance of these NoC interconnects have become a significant factor.The authors aim to reduce the leakage power consumption of NoC buffers by the use of non‐volatile spin transfer torque random access memory (STT‐RAM)‐based buffers. STT‐RAM technology has the advantages of high density and low leakage but suffers from low endurance. This low endurance has an impact on the lifetime of the router on the whole due to unwanted write‐variations governed by virtual channel (VC) allocation policies. Here various VC allocation policies that help the uniform distribution of the writes across the buffers are proposed. Iso‐capacity and iso‐area‐based alternatives to replace SRAM buffers with STT‐RAM buffers are also presented. Pure STT‐RAM buffers, however, impact the network latency. To mitigate this, a hybrid variant of the proposed policies which uses alternative VCs made of SRAM technology in the case of heavy network traffic is proposed. Experimental evaluation of full system simulation shows that proposed policies reduce the write variation by 99% and improve lifetime by 3.2 times and 1093 times, respectively. Also a 55.5% gain in the energy delay product is obtained.