State retained dual‐Vth feedback sleeper‐stack for leakage reduction. Issue 1 (3rd December 2018)

• Record Type: Journal Article
• Authors: Sreekala, Kollaparampil Somasekharan; Krishnakumar, Sukumarapillai
• Is Part Of: IET computers & digital techniques. Volume 13:Issue 1(2019)
• Page Start: 1
• Page End: 10
• Publication Date: 2018-12-03
• Subjects: circuit feedback -- delay circuits -- nanoelectronics -- low‐power electronics -- logic circuits -- logic design; state retained dual‐voltage threshold feedback sleeper‐stack -- leakage power reduction -- nanoscale devices -- leakage power problem -- low power circuit design -- delay efficient circuit level leakage reduction technique -- deep submicron technology -- DSM technology -- FS‐S -- exact logic state saving -- power‐delay product -- BSIM4 predictive technology model parameters -- logic circuits -- NAND3 gate -- C17 circuit -- size 45 nm; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.0009
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : With the advent of nanoscale devices, due to the problems of leakage power has grown enormously. Reducing leakage power is one of the main challenges in the design of low power circuits. This study presents a delay efficient circuit level leakage reduction technique, which uses dual‐ V th named 'Feedback Sleeper‐Stack (FS‐S)' for deep submicron (DSM) technology. FS‐S is proposed in order to reduce leakage power dramatically while saving exact logic state. An analytical RC delay model of the FS‐S is derived. Comparisons are then carried out in terms of leakage power, total power, delay, area, and power–delay product to the available leakage reduction techniques. 45 nm BSIM4 Predictive Technology Model parameters are used to estimate the changes in power and delay. FS‐S is applied to three generic logic circuits to show that the proposed technique is suitable for general logic circuits. Results show that chain of four inverters, NAND3 gate, and C17 circuit with dual‐ V th FS‐S give 15, 62, and 90% performance levels, respectively, over base case circuit under iso‐area condition.