Fighting stochastic variability in a D‐type flip‐flop with transistor‐level reconfiguration. Issue 4 (1st July 2015)

• Record Type: Journal Article
• Authors: Trefzer, Martin A.; Walker, James A.; Bale, Simon J.; Tyrrell, Andy M.
• Is Part Of: IET computers & digital techniques. Volume 9:Issue 4(2015)
• Page Start: 190
• Page End: 196
• Publication Date: 2015-07-01
• Subjects: flip‐flops -- MOSFET -- field programmable gate arrays; D‐type flip‐flop timing characteristics -- intrinsic stochastic variability -- design optimisation case study -- technology process -- multireconfigurable architecture -- field programmable gate array -- next‐generation FPGA architecture -- gate level -- transistor level configuration options -- hardware VLSI prototype -- virtual prototype -- simulation program -- integrated circuit emphasis -- statistically enhanced high performance metal gate MOSFET compact models -- gold standard simulations -- prefabrication verification -- programmable analogue architecture -- digital array architecture -- post‐fabrication transistor‐level optimisation -- operating point -- size 25 nm; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2014.0146
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : In this study, the authors present a design optimisation case study of D‐type flip‐flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi‐reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre‐fabrication verification. A D‐type flip‐flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next‐generation FPGA architecture that can recover yield using post‐fabrication transistor‐level optimisation in addition to adjusting the operating point of mapped designs.