Multi‐objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs. Issue 4 (19th February 2019)

• Record Type: Journal Article
• Authors: Wang, Yuan; Trefzer, Martin A.; Bale, Simon J.; Walker, James A.; Tyrrell, Andy M.
• Is Part Of: IET computers & digital techniques. Volume 13:Issue 4(2019)
• Page Start: 273
• Page End: 281
• Publication Date: 2019-02-19
• Subjects: field programmable gate arrays -- logic design -- genetic algorithms -- network routing -- integrated circuit design -- timing circuits -- electronic design automation; flexible EDA flow -- interconnect minimisation -- place‐and‐route process -- configurable logic blocks -- field programmable gate array -- timing driven circuit clustering -- multiobjective optimisation algorithm -- real‐world circuit design -- FPGA‐related literature -- Golden 20 MCNC benchmark circuits -- CLB utilisation -- CLB input bandwidth constraints -- multiobjective genetic algorithm -- time optimising circuit performance parameters -- FPGA CAD flow; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5115
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place‐and‐route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g. power and delay. In this study, the authors present a method based on multi‐objective genetic algorithm (MOGA) to facilitate circuit clustering. They address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. The authors' new approach has been validated using the 'Golden 20' MCNC benchmark circuits that are regularly used in FPGA‐related literature. The results show that the method proposed in this study achieves improvements of up to 50% in clustering, routability and timing when compared to state‐of‐the‐art approaches including VPack, T‐VPack, RPack, DPack, HDPack, MOPack and iRAC. The key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real‐world circuit design on FPGA, providing device utilisation at increased design performance.